The present invention generally relates to a circuit arrangement of a semiconductor integrated circuit device, and more particularly to improvements in circuit arrangements of a semiconductor integrated circuit device, such as a gate array device or a standard cell device, suitable for a matrix probing test.
There is known a semiconductor integrated circuit device called a logic LSI of a plurality of column shaped logic cell arrays, each having logic cells arranged into columns. One or more monitor points are provided in each of the logic cells. The logic cells are mutually coupled by interconnection lines to thereby provide desired logic circuits. There is also known a logic LSIs having column shaped basic cell arrays, each having a plurality of basic cells.
The recent advance of fabricating such logic LSIs makes it possible to provide a drastically increased number of logic cells arranged in one chip. Currently, it is possible to arrange logic LSIs having tens to hundreds of thousands of logic cells on a single chip. As an increased number of logic cells is provided, it becomes difficult to test logic LSIs. In order to test logic LSIs effectively and efficiently, there is proposed a logic LSI having a built-in test circuit. Normally, a test circuit built in a logic LSI is used for carrying out a good/fail judgment of internal circuits, debugging of logic design and analysis of faults. The above-mentioned situations hold true for logic LSIs having column shaped basic cell arrays.
Japanese Laid-Open Patent Application No. 61-42934 proposes a semiconductor integrated circuit device having a built-in test circuit. Referring to FIG. 1, there is illustrated the outline of the proposed device. A plurality of logic cells 2 are formed on a semiconductor chip 1. A built-in test circuit is composed of row select lines 3, column read lines 4, switch elements 5, a row select ring counter 6, a column select ring counter 7, a data selector 8, a row select clock input terminal 9, a column select clock input terminal 10 and a monitor output terminal 11. The logic cells 2 are interconnected on the basis of a user's design or specification in order to provide desired logic circuits. For the sake of simplicity, such interconnections are not illustrated in FIG. 1.
Output terminals of the logic cells 2 are connected to the column read lines 4 via the switch elements 5. The row select ring counter 6 selects one of the row select lines 3, and the column select ring counter 7 selects one of the column select lines 3, so that the logic cells 2 are selected one by one. The logic state of the output terminal of a selected logic cell 2 is output to the monitor output terminal 11 via the data selector 8. In this way, information about the states of the output terminals of the logic cells 2 is obtained at the monitor output terminal 11 and used for determining whether or not desired logic circuits operate correctly.
The above-mentioned test method is called a matrix proving method or simply an MP method. According to the matrix probing method, it is possible to read out the logic state of each logic cell 2. Thus, it is possible to design logic circuits easily, as compared with a conventional scan path method which uses flip-flops. In addition, the reliability of the matrix probing method is high.
In conventional logic LSIs as described above, the row select lines 3 are provided for the respective rows, and the column read lines 4 are provided for the respective columns. This causes a problem in that the wiring lines are not arranged efficiently and sometimes prevents the formation of the interconnection lines. Another problem arises from the fact that each of the rows has the same number of logic cells, each having one monitor point. Thus, the arrangement shown in FIG. 1 is not applied directly to a standard cell array device having various column shaped logic cell arrays in which one or more different types of logic cells having different areas are arranged and one or more monitor points are provided in the respective logic cell arrays. In order to fabricate such a standard cell array device on the basis of the concept of the arrangement shown in FIG. 1, it is necessary to provide a number of column read lines equal to a number of monitor points contained in one of the logic cell arrays having a maximum number of monitor points. This needs a large number of column read lines and makes it difficult to design the layout of interconnection lines for coupling the logic cells.